The present invention relates to a semiconductor device using polycrystalline silicon resistors having only a small resistance value deviation, and whose resistance varies with a change in temperature at a desired level (including wherein the resistance value is substantially independent of a change in temperature), e.g., in the temperature range of use of the device.
With respect to the prior art concerned with resistors using polycrystalline silicon, IEEE Transactions on Electron Devices, ED-28, No. 7 (1981), pp. 818-830, and Gray and Meyer, Analysis and Design of Analog Integrated Circuits, 2d Ed. (1984), John Wiley & Sons, Inc. disclose an arrangement of making one of the following a resistor, namely, (1) an impurity diffusion region in a semiconductor substrate, and (2) a polycrystalline silicon layer on a dielectric film. FIGS. 20-22 of the present application are sectional views of these structures, wherein numeral 1 denotes a silicon substrate (e.g., monocrystalline silicon), 2 and 4 silicon dioxide films, 3a a polycrystalline silicon layer of small grain size, 3b a polycrystalline silicon layer of large grain size, 7 an aluminum electrode, and 8 a P-type impurity diffusion region.
However, the resistance value of a resistor using polycrystalline silicon drastically varies with temperature, in a temperature range of use of the resistor (e.g., -20.degree. C. to 150.degree. C.), and this poses a serious problem in designing circuits in a case where the resistors of that sort are employed in integrated circuits.
In order to meet the situation above, (1) Japanese Patent Laid-Open Nos. 182259/1983, 74466/1985 and 116160/1985 disclose method of controlling polycrystalline grain size; (2) Japanese Patent Laid-Open No. 263367/1991 discloses the use of polycrystalline silicon containing impurities whose temperature coefficient of resistance in the high concentration area is positive and negative, whereas Japanese Patent Laid-Open No. 285668/1990 discloses a method of forming a state in a silicon bandgap by irradiating the polycrystalline silicon with charged particles; (3) Japanese Patent Laid-Open Nos. 191062/1986 and 268462/1990 disclose a method of coupling a polycrystalline silicon resistor layer having a negative temperature coefficient to a single-crystal silicon region (in a substrate) having a positive temperature coefficient, in series or parallel; and (4) Japanese Patent Laid-Open No. 51957/1986 discloses an arrangement of making a resistor from a polycrystalline silicon film and a doped region in a silicon member, the resistor including a polycrystalline silicon film and single crystal silicon.
The foregoing disclosed structures have problems in providing resistors of desired resistance values and with no (or substantially no) temperature dependence of resistance over the temperature range of use of the resistor. For example, where only a single layer or single region is used, it is difficult to both control the resistance value to a desired value, and to provide a temperature dependence of resistance that is substantially zero. Moreover, fabrication difficulties arise, or the manufacturing is made more complex, by electrically connecting a semiconductor region in, e.g., a single-crystal silicon substrate to a polycrystalline silicon layer (either by forming the polycrystalline silicon directly on the semiconductor region or electrically connecting an overlying polycrystalline silicon layer to a region in a single-crystal silicon substrate).
Moreover, in the methods discussed above the temperature dependence of such a resistor that uses polycrystalline silicon needs to be improved with respect to a specific resistance value. However, the improvement of the temperature dependence with respect to any given specific resistance value cannot technically be provided, and this means different processes of manufacture will have to be adopted for different resistance values of different resistors, even where the different resistors are on a same substrate of a same semiconductor device.
Moreover, there arises a problem in that polycrystalline silicon resistors different in resistance value are difficult to form on one and the same substrate. In other words, a method of manufacturing extremely small polycrystalline silicon resistors excellent in temperature dependence remains nonexistent. The method of (1), with reference to Japanese Patent Laid-Open No. 182259/1993, as noted previously, for example, has disadvantages including a poor affinity between the process and other resistors because the grain size is controlled by heat treatment, and difficulties arise in simultaneously improving temperature dependence of at least two resistors which are different in resistivity. In the case of the method with reference to Japanese Patent Laid-Open No. 74466/1985, a shortcoming is that the number of process steps increases as laser annealing and hydrogen plasma treatment are added, simultaneously with the limitation of heat treatment after the formation of resistance. As for the method with reference to Japanese Patent Laid-Open No. 116160/1985, a shortcoming lies in the fact that the temperature dependence is determined by, for example, resistivity, and that the effect of improvement is attainable only at high resistivity. Further, the method of (2), with reference to Japanese Patent Laid-Open No. 263367/1991, as noted above, has a disadvantage in poor processing stability because the segregation coefficient is affected by impurity concentration and the history of heating the resistor. Regarding the method with reference to Japanese Patent Laid-Open No. 285668/1990, a shortcoming includes the necessity of introducing crystal defects into polycrystalline silicon with excellent controllability, and its applicability to only high resistivity with a greater resistance component on the grain boundary. The method of (3) also poses such problems that (a) since two kinds of resistors are connected together via an electrode, deviation of characteristics tends to increase in comparison with the use of a single resistor, because deviation in resistance becomes equal to the sum of deviations of characteristics of both resistors, and (b) not only the number or process steps but also the area occupied thereby increases. Further, the method of (4) is disadvantageous in that since a laser beam is used to cause liquid phase epitaxial growth, the physical position of a resistor is restricted, and this makes difficult the industrial application of this method to LSIs.